Generally, semiconductor devices include a plurality of integrated circuits (ICs). ICs can be useful for many applications including computers and electronic equipment and they can contain millions of transistors and other circuit elements that can be fabricated on a single semiconductor chip. For device functionality, a complex of signal paths will typically be routed to connect the circuit elements distributed on the surface of the semiconductor device. Efficient routing of these signals across the device can become more difficult as the complexity and number of ICs is increased. Thus, the formation of multi-level or multi-layered interconnect schemes, including dual damascene, has become more desirable due to their efficacy in providing high-speed signal routing patterns between a large number of transistors on a single semiconductor chip.
In fabricating IC wiring with a multi-level scheme, an electrically insulating material (oftentimes referred to as a dielectric material) such as SiO2, will normally be patterned to create openings for conductive lines and/or vias using photolithography and etching. These openings formed into the dielectric material are typically filled with a conductive material such as Cu or Al to interconnect the active device regions of the ICs. After the filling process, the semiconductor device is generally planarized by chemical-mechanical polishing. Interconnect structures of the dual damascene type are highly preferred in the industry.
The patterning of conventional insulating materials such as SiO2 includes the use of many layers of different patterning and masking materials (typically up to 7 different layers of materials are employed in the prior art) that are formed atop the insulating layer prior to patterning. For example, a nitride hard mask, a silicon oxide hard mask, and a metal hard mask may all be used in patterning a single insulating layer of a typical interconnect structure. After forming the masking layers atop the insulating material, a photoresist and an anti-reflective coating are generally applied to the uppermost surface of the masking layers. The photoresist is then patterned by lithography and thereafter a series of etching steps are employed to first transfer the pattern from the photoresist to each of the masking layers and thereafter to the insulating layer. Furthermore, these masking layers have to be removed after patterning. Therefore, the prior art process of patterning a dielectric material is a very inefficient process.
In recent years, conventional insulating materials such as SiO2 are being phased out and replaced with dielectric materials that have a low-dielectric constant (low-k) associated therewith. The term “low-k” denotes a dielectric material that has a dielectric constant lower than SiO2, i.e., <3.9. For example, various polymer dielectrics such as polyarylenes and carbon-doped organosilicates have been developed and are currently being integrated into various IC interconnect structures. These low-k dielectrics are particularly advantageous for use as an interconnect dielectric because they significantly reduce signal delay and cross-talk in interconnect structures due to their lower dielectric constant.
Despite this advantage, prior art low-k dielectrics are typically photoinactive; therefore the patterning thereof requires the above mentioned multilayer masking scheme. Prior art multilayer masking schemes of the type mentioned above are extremely insufficient because: (i) they need many layers of sacrificial materials; (ii) each individual masking layer needs to be removed after patterning; (iii) the various masking layers sometimes increase the effective dielectric constant of the IC; and (iv) they increase integration complexity and manufacturing costs (i.e., a need for separate and expensive deposition and etching tools).
In addition, a separate photoresist is typically needed to pattern the same. Specifically, the patterning of prior art photoinactive low-k materials requires first patterning of the photoresist and thereafter various etching steps which transfer the pattern from the photoresist into each of the masking layers before ultimately patterning of the low-k dielectric.
In the prior art, silsesquioxane polymers containing base sensitive functional groups are known. See, for example, U.S. Pat. No. 5,789,460 to Harkness, et al.; U.S. Pat. No. 5,891,529 to Harkness, et al.; U.S. Pat. No. 5,820,944, to Harkness, et al.; U.S. Pat. No. 5,861,235 to Harkness, et al.; U.S. Pat. No. 6,096,483 to Harkness, et al.; U.S. Pat. No. 6,051,625 to Harkness, et al.; and U.S. Pat. No. 6,258,506 to Harkness, et al. The base catalyzed polymers described in the prior art suffer the following drawbacks: (i) they have a low resolution; (ii) they have a low sensitivity; and (iii) they do not provide a patterned low-k material.
In view of the state of the art mentioned hereinabove, there is a continued need for providing a low-k dielectric material that can be used as an inter-level or intra-level dielectric of an interconnect structure, yet does not require numerous materials (i.e., masking layers, photoresist and ARC) and processing steps for patterning the same. That is, a material is needed which combines the functions of a photoresist and a conventional low-k dielectric into a single material. Such a material would greatly reduce the integration complexity and processing steps required in the prior art to provide a patterned low-k interconnect dielectric. Separate photoresist (or masking layers) and related patterning processes (deposition and etching tools) would not be needed since the material would be capable of being patterned itself.